4.2 含有无关项的序列检测

`timescale 1ns/1ns
module sequence_detect_2(
  input clk,
  input rst_n,
  input a,
  output reg match
);
  parameter idle = 4'b0000;
  parameter s0 = 4'b0001;
  parameter s1 = 4'b0010;
  parameter s2 = 4'b0011;
  parameter s3 = 4'b0100;
  parameter s4 = 4'b0101;
  parameter s5 = 4'b0110;
  parameter s6 = 4'b0111;
  parameter s7 = 4'b1000;
  parameter s8 = 4'b1001;
  reg [8:0] cs;
  reg [8:0] ns;
  always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
      cs <= 9'b000000000;
    end
    else begin
      cs <= ns;
    end
  end
  always @(*) begin
    case(cs)
      idle : ns = (a == 1)? idle : s0;
      s0 : ns = (a == 1)? s1 : s0;
      s1 : ns = (a == 1)? s2 : s0;
      s2 : ns = s3;
      s3 : ns = s4;
      s4 : ns = s5;
      s5 : ns = (a == 1)? s6 : s0;
      s6 : ns = (a == 1)? s7 : s0;
      s7 : ns = (a == 1)? idle : s8;
      s8 : ns = (a == 1)? s1 : s0;
      default : ns = idle;
    endcase
  end
  wire match_tmp;
  assign match_tmp = (cs == s8);
  always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
      match <= 1'b0;
    end
    else begin
      match <= match_tmp;
    end
  end
endmodule

由于其中包含了一些无关的序列，所以不需要进行输入状态的判断。